Cypress Semiconductor /psoc63 /SRSS /CLK_FLL_CONFIG4

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Interpret as CLK_FLL_CONFIG4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CCO_LIMIT0 (RANGE0)CCO_RANGE 0CCO_FREQ0 (CCO_HW_UPDATE_DIS)CCO_HW_UPDATE_DIS 0 (CCO_ENABLE)CCO_ENABLE

CCO_RANGE=RANGE0

Description

FLL Configuration Register 4

Fields

CCO_LIMIT

Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)

CCO_RANGE

Frequency range of CCO

0 (RANGE0): Target frequency is in range [48, 64) MHz

1 (RANGE1): Target frequency is in range [64, 85) MHz

2 (RANGE2): Target frequency is in range [85, 113) MHz

3 (RANGE3): Target frequency is in range [113, 150) MHz

4 (RANGE4): Target frequency is in range [150, 200] MHz

CCO_FREQ

CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range.

CCO_HW_UPDATE_DIS

Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation.

CCO_ENABLE

Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on

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